Since variation in threshold voltage VT of a MOS transistor increases along with miniaturization, operation speed of the MOS transistor on a chip varies increasingly. This variation in speed becomes more pronounced as operating voltage VDD thereof drops. The increase in the threshold voltage VT also causes an increase in offset voltage of a sense amplifier used in dynamic random access memory (referred to below as DRAM) and makes sensing operations unstable. Here, an offset voltage is the difference in threshold voltage VT of 2 cross-coupled MOS transistors that perform a signal amplification operation. Furthermore, since a sense amplifier operates at a low voltage of VDD/2 at an initial stage of an amplification operation, high speed operation becomes increasingly difficult as the threshold voltage VT variation increases. It is known that this offset voltage is reduced by decreasing impurities in a MOS transistor channel. Moreover, since the threshold voltage VT of the MOS transistor is reduced by decreasing the impurities, it is possible to operate the MOS at high speed, even with low voltage. As a result, a sense amplifier can also operate at high speed even with a low voltage. However, there is a problem in that, since a sub-threshold current increases when the threshold voltage VT is reduced, power increases when data is retained. In the present specification, a sub-threshold current and a leakage current are used with the same meaning.
Patent Document 1 describes an example of a sense amplifier SA that simultaneously realizes offset voltage reduction, high speed sensing operation, and low power data retention. The SA and a related circuit described in Patent Document 1 are shown in FIG. 27. The SA 116 is configured by an NMOS amplifier (NSA 119) formed from 4 NMOS transistors (Q1, Q2, Q3, and Q4), an NMOS latch (NL 118, a type of cross coupled amplifier) formed from 2 cross-coupled NMOS transistors (Q7 and Q8), and a PMOS amplifier (PSA 117) formed from 2 cross-coupled PMOS transistors (Q5 and Q6). With respect to the NSA 119, Q3 and Q4 are connected to respective drains of the cross-coupled Q1 and Q2. A feature of this SA 116 is that a threshold voltage VT of Q1 and Q2 is set to be smaller than other voltages. As mentioned above, since the offset voltage is small in an MOS with a small threshold voltage VT, by performing a sensing operation by the NSA 119, a stable and high speed sensing operation is possible even with low voltage. When data is retained, by the NSA 119 being inactive and the NL 118 retaining the data, reduction of data retention power is possible.
[Patent Document 1]
    JP Patent Kokai Publication No. JP-P2008-171476A, which corresponds to US Patent Application Publication No. US2008/0175084A1.